This invention relates generally to integrated circuits, and more particularly to heterogeneous stacked integrated circuit testing.
Computer chips and integrated chip stacks are tested during the manufacturing process, as well as post manufacturing to ensure high quality and reliability. One type of such testing (sometimes referred to as “burn-in”) involves stressing the chip stacks with the varying levels of voltages and temperatures to ensure the chip stacks can withstand a minimum level of such applied stress. Performing this testing prior to shipping the chip stacks can minimize early failures, referred to as “infant mortality.”
However, burn-in testing is becoming increasingly challenging due to various factors. For example, test procedures performed on one particular component can damage other more sensitive, nearby components on the chip or stack layers, thereby reducing the overall yield of the final chip stack product. Also, controlling on-chip temperatures during the high-voltage, high temperature burn-in stages can be difficult due to increases in on-chip power dissipation and temperature/leakage dependency. As a result, many stress testing techniques apply shorter periods of high-temperatures/high-voltages to components in order to minimize the likelihood of such conditions.
In addition, testing processes for high-power, three-dimensional (3D) microprocessor architectures also present significant challenges. In computer chip manufacturing, 3D stacked layers of components (e.g., processing chips and memory) are combined in a way that decreases the distance that data must travel between the components. As a result, overall system performance can be improved by leveraging the increased interconnectivity inherent in 3D stacks, particularly in a heterogeneous stacking context (e.g., disparate technologies, different technology generations, and various circuit and layer types from a functional perspective). Providing a stack-level test configuration for such a range components is challenging since sometimes a test requirement for a layer can be completely harmful for a sensitive layer nearby. Furthermore, since the on-chip temperatures are already high in 3D chip stacks, the additional thermal and reliability stress in burn-in testing can very easily damage parts of the processor. The margin of operation for such stack level burn-in is limited, thereby rendering burn-in testing impractical in many cases.
Further, heterogeneous 3D chip stacks incorporate device layers with disparate technologies (e.g. MEMS, SOI), different technology generations, such as 65 nm and 45 nm) and different characteristics (e.g., analog, digital, variations in chip sizes, aspect ratios, and chip thicknesses, as well as varying operating point specifications, such as clock frequencies, applied voltages, and characteristics of wiring layers). As a result, the sensitivity to burn-in in such heterogeneous stacks can be quite high (e.g., while stressing one of the layers in the stack, another layer, which is more sensitive, may become damaged in the process).
While wafer-level or single stratum test data can be very useful and informative in the testing process, it is insufficient for 3D chip stacks. The reliability characteristics of the 3D chip stack may be impacted by the assembly stages that typically involve abrasive or higher risk, steps such as chemical mechanical planarization (CMP), high-temperatures, compression bonding, and the like, with potentially negative implications on the underlying device layers.